Kohya S
f2bc820133
support weighted captions for SD/SDXL
2024-10-11 08:48:55 +09:00
Kohya S
886f75345c
support weighted captions for sdxl LoRA and fine tuning
2024-10-10 08:27:15 +09:00
Kohya S
126159f7c4
Merge branch 'sd3' into sdxl-ctrl-net
2024-10-07 20:39:53 +09:00
Kohya S
83e3048cb0
load Diffusers format, check schnell/dev
2024-10-06 21:32:21 +09:00
Kohya S
ba08a89894
call optimizer eval/train for sample_at_first, also set train after resuming closes #1667
2024-10-04 20:35:16 +09:00
Kohya S
c2440f9e53
fix cond image normlization, add independent LR for control
2024-10-03 21:32:21 +09:00
Kohya S
793999d116
sample generation in SDXL ControlNet training
2024-09-30 23:39:32 +09:00
Kohya S
d78f6a775c
Merge branch 'sd3' into sdxl-ctrl-net
2024-09-29 23:23:07 +09:00
Kohya S
8bea039a8d
Merge branch 'dev' into sd3
2024-09-29 23:19:12 +09:00
Kohya S
012e7e63a5
fix to work linear/cosine scheduler closes #1651 ref #1393
2024-09-29 23:18:16 +09:00
Kohya S
0243c65877
fix typo
2024-09-29 23:09:56 +09:00
Kohya S
8919b31145
use original ControlNet instead of Diffusers
2024-09-29 23:07:34 +09:00
青龍聖者@bdsqlsz
e0c3630203
Support Sdxl Controlnet ( #1648 )
...
* Create sdxl_train_controlnet.py
* add fuse_background_pass
* Update sdxl_train_controlnet.py
* add fuse and fix error
* update
* Update sdxl_train_controlnet.py
* Update sdxl_train_controlnet.py
* Update sdxl_train_controlnet.py
* update
* Update sdxl_train_controlnet.py
2024-09-29 10:11:15 +09:00
Kohya S
d050638571
Merge branch 'dev' into sd3
2024-09-29 10:00:01 +09:00
Kohya S
1567549220
update help text #1632
2024-09-29 09:51:36 +09:00
Kohya S
fe2aa32484
adjust min/max bucket reso divisible by reso steps #1632
2024-09-29 09:49:25 +09:00
Kohya S
1a0f5b0c38
re-fix sample generation is not working in FLUX1 split mode #1647
2024-09-29 00:35:29 +09:00
Kohya S
822fe57859
add workaround for 'Some tensors share memory' error #1614
2024-09-28 20:57:27 +09:00
Kohya S
a9aa52658a
fix sample generation is not working in FLUX1 fine tuning #1647
2024-09-28 17:12:56 +09:00
Kohya S
3ebb65f945
Merge branch 'dev' into sd3
2024-09-26 21:41:25 +09:00
Kohya S
ce49ced699
update readme
2024-09-26 21:37:40 +09:00
Kohya S
a94bc84dec
fix to work bitsandbytes optimizers with full path #1640
2024-09-26 21:37:31 +09:00
Kohya S.
4296e286b8
Merge pull request #1640 from sdbds/ademamix8bit
...
New optimizer:AdEMAMix8bit and PagedAdEMAMix8bit
2024-09-26 21:20:19 +09:00
Kohya S
392e8dedd8
fix flip_aug, alpha_mask, random_crop issue in caching in caching strategy
2024-09-26 21:14:11 +09:00
Kohya S
2cd6aa281c
Merge branch 'dev' into sd3
2024-09-26 20:52:08 +09:00
Kohya S
bf91bea2e4
fix flip_aug, alpha_mask, random_crop issue in caching
2024-09-26 20:51:40 +09:00
Kohya S
da94fd934e
fix typos
2024-09-26 08:27:48 +09:00
Kohya S
56a7bc171d
new block swap for FLUX.1 fine tuning
2024-09-26 08:26:31 +09:00
sdbds
1beddd84e5
delete code for cleaning
2024-09-25 22:58:26 +08:00
Kohya S
65fb69f808
Merge branch 'dev' into sd3
2024-09-25 20:56:16 +09:00
Kohya S
e74f58148c
update README
2024-09-25 20:55:50 +09:00
Kohya S.
c1d16a76d6
Merge pull request #1628 from recris/huber-timesteps
...
Make timesteps work in the standard way when Huber loss is used
2024-09-25 20:52:55 +09:00
sdbds
ab7b231870
init
2024-09-25 19:38:52 +08:00
Kohya S.
fba769222b
Merge branch 'dev' into sd3
2024-09-23 21:20:02 +09:00
Kohya S
29177d2f03
retain alpha in pil_resize backport #1619
2024-09-23 21:14:03 +09:00
recris
e1f23af1bc
make timestep sampling behave in the standard way when huber loss is used
2024-09-21 13:21:56 +01:00
Kohya S.
95ff9dba0c
Merge pull request #1619 from emcmanus/patch-1
...
Retain alpha in `pil_resize` for `--alpha_mask`
2024-09-20 22:24:49 +09:00
Kohya S
583d4a436c
add compatibility for int LR (D-Adaptation etc.) #1620
2024-09-20 22:22:24 +09:00
Kohya S.
24f8975fb7
Merge pull request #1620 from Akegarasu/sd3
...
fix: backward compatibility for text_encoder_lr
2024-09-20 22:16:39 +09:00
Akegarasu
0535cd29b9
fix: backward compatibility for text_encoder_lr
2024-09-20 10:05:22 +08:00
Ed McManus
de4bb657b0
Update utils.py
...
Cleanup
2024-09-19 14:38:32 -07:00
Ed McManus
3957372ded
Retain alpha in pil_resize
...
Currently the alpha channel is dropped by `pil_resize()` when `--alpha_mask` is supplied and the image width does not exceed the bucket.
This codepath is entered on the last line, here:
```
def trim_and_resize_if_required(
random_crop: bool, image: np.ndarray, reso, resized_size: Tuple[int, int]
) -> Tuple[np.ndarray, Tuple[int, int], Tuple[int, int, int, int]]:
image_height, image_width = image.shape[0:2]
original_size = (image_width, image_height) # size before resize
if image_width != resized_size[0] or image_height != resized_size[1]:
# リサイズする
if image_width > resized_size[0] and image_height > resized_size[1]:
image = cv2.resize(image, resized_size, interpolation=cv2.INTER_AREA) # INTER_AREAでやりたいのでcv2でリサイズ
else:
image = pil_resize(image, resized_size)
```
2024-09-19 14:30:03 -07:00
Kohya S
b844c70d14
Merge branch 'dev' into sd3
2024-09-19 21:51:33 +09:00
Kohya S.
0b7927e50b
Merge pull request #1615 from Maru-mee/patch-1
...
Bug fix: alpha_mask load
2024-09-19 21:49:49 +09:00
Kohya S
706a48d50e
Merge branch 'dev' into sd3
2024-09-19 21:15:39 +09:00
Kohya S
d7e14721e2
Merge branch 'main' into dev
2024-09-19 21:15:19 +09:00
Kohya S
9c757c2fba
fix SDXL block index to match LBW
2024-09-19 21:14:57 +09:00
Maru-mee
e7040669bc
Bug fix: alpha_mask load
2024-09-19 15:47:06 +09:00
Kohya S
1286e00bb0
fix to call train/eval in schedulefree #1605
2024-09-18 21:31:54 +09:00
Kohya S
e74502117b
update README
2024-09-18 08:04:32 +09:00
